In-depth analysis of renesas m16c/6s: 16 places of a highly integrated sectionMonophone
In the world of electronic engineers, single-piece machines are an indispensable core component. The renesas m16c/6s series single machines have emerged in numerous single machines with their unique performance and rich functionality. Today, we're going to go deep into this single machine and understand its characteristics, functions and applications。
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Overview of products
The renesas m16c/6s series is a highly integrated 16-bit cmos microcomputer with a 64-step plastic model of lqfp. It integrates plc (electrical line communication) modem core and afe (simulation front end) using it800 plc modem technology developed by yitran communications ltd. The m16c/60 series cpu core ensures high-code efficiency and high-speed operations, while the dcsk (discretion key transfer) amplification technology used at the it800 modem core allows extremely robust communications to be achieved on existing power lines at a data rate of up to 7. 5 kbps. The series is consistent with global regulations (fcc part 15, arib and cenelec bands) and appliesSmart measuresAndFamily networkAll kinds of narrowband applications。
Performance summary project details
Cpu
Number of basic instructions 91; minimum instruction time 65. 1 ns(f(bclk)=15. 36 mhz, vcc = 3. 0 v - 3. 6 v); operating mode is single chip mode
Memory space
1m bytes
Memory capacity
Rom: see list of products; ram: 24k bytes
External
Port: input/output 21 lead foot, enter 1 lead foot; multifunctional timer: timer a is 16 bit x 5 channel; serial i/o: 2 channel hourly synchronisation, uart, i2c bus (1), 1 channel uart, i2c bus (1), 2 channel hourly synchronization (of which 1 channel is internal to it800); dmac:2 channel; watchdog timer: 15 bits 1 channel (with pre-frequency); interrupted: 21 internal and 3 external sources, 4 software sources, 7 level
Clock generation circuits
Two circuits. Main clocks generate pll compositers. Device
Electrical characteristics
Power pressure 3. 0 v - 3. 6 v; power consumption 70 ma (vcc = vca = 3. 3 v, f (xin) = 5. 12 mhz)
Flash version
3. 0v - 3. 6v (topr = 0 - 60°c); 100 times programming/elimination durability; 70 ma (vcc = vca = 3. 3v, f (xin) = 5. 12 mhz); working environment temperature - 20 - 85°c, -40 - 85°c, -40 - 105°c
Cover
64 boot plastic model lqfp
Internal structure and functional module 1. Memory
Memory address space ranges from 0000016 to f16 for a total of 1m bytes. Internal roms are allocated to low addresses starting from address f 16, e. G. Within 96 k bytes at address e800016 to f16. The fixed interruption vector schedule is assigned at the fffdc16 address to f16 and the internal ram is allocated from the address 0040016 to the high address, e. G. The internal ram is assigned at the address 0040016 to 063ff16 in 24k bytes. The sfr (special function register) is assigned to the address 0. 00016 to 003ff16, and the special page vector table is assigned to the address ffe0016 to fffdb16。
2. Central processing module (cpu)
Cpu has 13 senders, of which r0, r1, r2, r3, a0, a1 and fb form the depository group, with two. Different depository devices have different functions, such as data repository (r0-r3) is used mainly for data transmission and arithmetic/logical operations; address repository (a0, a1) is used for indirect address and address repository addresses; frame-based repository (fb) is used for relative fb addresses。
3. Special feature register (sfr)
Sfr consists of multiple repositories that control processor modes, system clocks, address matching interruptions, door dog timers, dma, etc. Each repository has a specific initial value after it has been duplicated, and the setting of certain bits will affect the opening or closing of the corresponding function. For example, the pm0 register is used to set the processor mode and the cm0 and cm1 register is used to control the system clock。
4. Reinstatement
M16c/6s has four types of recognizance: hardware recoupation, software recoupation, guard dog timing and oscillation stop detection. The repositioning of the hardware is achieved through the reset-led foot, and when the power voltage is in the recommended working conditions and the reset-led foot is a “l” signal, the flow is initiated, the shock circuit is initiated and the main clock starts to convulse. The reset of the software is achieved by setting pm03 to " 1 " for the pm0 repository. The guard dog timer reverts to pm12 at pm1 repository and is activated when the guard dog timer spills. The oscillation stopped detection at cm2 repository at cm27 position "0" and was detected when the main clock oscillation circuit stopped。
Processor mode
The processor mode is single chip mode only, with pm01-pm00 bit settings for the cnvss tab and pm0 register. The plc model is set by placing p15 at high electrical level during the reset period。
6. Clock generation circuits
The clock generation circuit consists of the main clock oscillating circuit and the oscillator on the plate. The main clock is provided by it800 with three times the number of hours xin (the main clock oscillator), which can be used as a source for cpu and external functional clocks. The oscillator clock is about 1 mhz and can also be used as a source for cpu and external functional clocks. A different clock frequency can be achieved by selecting a clock source and a frequency fraction from the relevant repository。
Interruption
Interruption divided into software and hardware interruptions. The software interruption occurs in the performance of a specific command and is a non-shield break, such as an undefined break in the command, a spill break, a break in the brk and an interruption in the int command. Hardware interruptions are classified as special interruptions and external disruptions, such as the dbc interruption, the timer interruption of the guard dog, the suspension of the oscillation and the interruption of the resonance detection, the one-step interruption and the address matching interruptions; the external interruption is the interruption of the shield, resulting from the internal functionality of the microcomputer. Interrupted vector consists of four bytes setting the starting address for each interrupted routine。
8. Watchdog timer
The watchdog timer is used to detect uncontrolled processes and improve system reliability. It consists of a 15-digit counter, which counts down the clocks after the splitting of the cpu clocks through the pre-alignment frequency. The pm12 of the pm1 repository can choose whether to create a request for an interruption or to perform a repositioning operation when the watch dog timer overflows。
9. Dmac (direct memory access controller)
Dmac allows data to be transmitted without cpu intervention, with two channels. On each dma request, dmac transmits a data (8 or 16 bits) from the source to the target address. The dma request can be triggered by a request for an interruption resulting from the writing of the dsr slot of the dmisl repository and the functionality specified by the dmisl repository。
10. Timers
There are five 16-bit timers, each of which can be operated independently. Timer a supports the timer model, the event counter model, the single-trigger timing mode and the pulse width mode (pwm). Through the taimr repository, you can select the mode required and set parameters such as counting sources, counting operations, etc。
11. Serial i/o
Serial i/o consists of five corridors: uart0-uart2, si/o3 and si/o4. Each uarti has a dedicated timer to generate transmission clocks, operating independently. (b) modes i/o, i/o (uart), special mode 1 (i2c) and special mode 2 are available。
Iii. Application of scene 1. Smart measurement
M16c/6s electrical line communication functions make it highly appropriate for intelligent measurement applications. Data transmission through power lines allows for remote data collection and monitoring of metering equipment such as meters, water meters, gas meters, etc., to improve the accuracy and efficiency of measurements。
2. Family networks
In the home network, m16c/6s can be used to connect various smart home devices such as smart lamps, smart home appliances, etc. Interconnection of equipment through electrical line communication to facilitate centralized control and management by users。
Use note 1. Storage settings
An immediate value should be set for a repository containing only places. When you change the register value, write the previous value to ram, modify the contents of the ram and then transfer the new value to the register。
2. Power control
When entering the waiting mode, insert the jmp. B directive before the wait directive to avoid the execution of a possible ram-inserted directive between the jmp. B and the wait directive, disable the possible dma transmission and insert at least four nop instructions after the wait directive. Inserts a jmp. B directive and at least four nop instructions as soon as you have set the cm1 repository at cm10 to 1。
3. Interruption generation factor changes
If the break generation factor is changed, it may result in an interruption of the ir slot in the control register to 1. The interrupted ir must be emptied after changing the interruption generation factor to be used。
4. Disruption of guard dog timer
Following a break in the doordog timer, the door-dog timer should be initialized。
5. Dmac
When certain conditions are met, the dmae and dmas slots in the dmicon repository are written as 1 and the initial state of dmai is ensured in the procedure。
Timer a
When setting parameters such as the mode, array source, counter value of the timer a, the tais position should be zero. When reading the tai repository during the counting process, care shall be taken of possible special circumstances。
7. Serial i/o
In the clock synchronization line i/o mode, the output level changes of rtsi can be used to notify the transmission side receipt readiness when the external clock is selected and the rts function is used. When transmitting and receiving data, meet the corresponding conditions and avoid spill errors。
Flash version
The memory address of the flash version of the id code and the romcp repository are very important, and error in data writing may result in flashing not being read and written. As the number of programming/wielding increases, the execution time of software commands increases. The software order may be interrupted by the repositioning of the hardware, the loss of electrical detection and the interruption of the guard dog timer, and the affected block must be erased before the order is re-executed。
The renesas m16c/6s series single machine, with its rich functionality and good performance, provides strong support for the design of electronic engineers in areas such as intelligent measurement, home network, etc. During their use, engineers need to be fully informed about their internal structures and functional modules and follow user-sensitive procedures to ensure the stable operation of the system. What problems have you encountered in using the m16c/6s series? Welcome to sharing your experiences and insights in the comment area。
